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| Introduction |
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The world of
programmable logic has come a long way from the days of
tens and hundreds of gates on a single gate array chip,
to millions today. It is amazing that these programmable
logic devices are competing with ASICs to deliver solutions
at lower NRE costs, lesser time and with greater flexibility
in terms of scalable designs. Today, lab-less design homes
with their engineering teams and design capabilities are
delivering solutions across telecommunications, signal
processing for sound and imaging, industrial, aerospace
and other domains. It is extraordinary that not only ASICs,
but FPGAs are also equally in demand for such applications
and in some cases preferred over ASICs.
ASL, with its team of aspiring engineers is a forerunner
in the field of FPGA designs. From the basics of translating
the specifications into Digital Block Level architecture
to realizing it using HDLs(VHDL/Verilog) and finally testing
it on an FPGA, has been the core line of work for our
team. |
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| The area of expertise: |
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The following are the technical areas that ASL has built
up its expertise on;
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| Digital
Design
HDL coding
Simulation (Functional/Timing with SDF
Back annotation)
Synthesis
Static Timing Analysis
Scripting (TCL)
System realization using FPGA with embedded
soft processor |
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| Intellectual Property
(IP) |
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The following are the specific developments as intellectual
property of ASL;
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| PPI - Programmable
Peripheral Interface (8255)
PIC - Programmable Interrupt Controller
(8259)
UART - Universal Asynchronous Receiver
Transmitter (8251)
USB 2.0 - Function Controller
IRIG -B |
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| Projects |
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Based on development in these areas, following specific
projects have been taken up:
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| i. Event
Logger |
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It is a GPS based Location
and Time stamp unit which logs a host of analog and digital
data as events from the platform of it use, be it a Rail
engine, a Road vehicle, or an Industrial process plant.
It uses an FPGA implementation on Altera platform together
with Embedded Soft Processor - NIOS. A host of interfaces
as below are provided:
UART
USB 2.0
Compact Flash
A/D Converter |
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| ii. Time Synchronization |
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It is used to synchronize
distributed networks in the Information Technology or
Telecom or Power sectors of Industry by extracting the
time information from the GPS strings and converting it
to IRIG-B data formats.
The unit works on FPGA implementation using Altera platform
and Embedded Soft Processor - NIOS. Following are the
interfaces provided:
IRIG
- B
UART
USB 2.0
Ethernet |
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| iii. Embedded Software
on NIOS |
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As a development project,
a powerful NIOS soft processor was used on which embedded
software was designed to serve applications such as event
logging, time synchronization, or multi-sensor integration
using FPGA platform. Drivers for following were also made
for this purpose;
FAT File
System
RS232 Serial Driver
USB Function Controller Bulk only
Compact Flash |
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| For
more details on projects, please email to : contact@asladvancedsys.in |
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© 2009 ASL Advanced Systems Pvt Ltd